General Electric IC660BBD022 Bus Transfer Protocol

The IC660BBD022  bus has strict regulations and requirements for technical indicators such as protocol, timing, load, electrical characteristics, and mechanical characteristics. Here is a brief introduction to the basic operating rules (or protocols) of IC660BBD022  bus:

(1) Basic bus transmission mechanism: A burst transmission includes one address period and one or several data periods.

(2) All signals except RST #, INTA #~INTD # are sampled on the rising edge of the clock.

(3) The data transmission on the PCI bus is basically controlled by three signal lines: Frame #, IRDY #, and TRDY #.

(4) When both Frame # and IRDY # are invalid, the interface is in an idle state. The first clock leading edge after the establishment of the Frame # signal is the address period, on which addresses and bus commands are transmitted; The next clock front begins one or more data periods. IRDY # and TRDY # perform a data transfer at the effective clock front.

(5) Whether it is the main device or the target device, once data transmission is promised, it must proceed until the completion of this transmission.

(6) The revocation of IC660BBD022  # and the establishment of IRDY # indicate that the main device is ready for the final data transmission. When the target device sends the TRDY # signal, it marks the completion of the final transmission.