Convolutional code is a commonly used error control encoding in deep space communication systems and wireless communication systems. VMIVME-7750-466000 overcomes the disadvantage of block coding that results in the loss of relevant information between groups. Convolutional codes (2, 1, 8) have been widely used in 2G and 3G communication systems. The forward channel of CDMA/IS-95 system [3] and the forward and backward links of CDMA20001x both use convolutional codes with a generating polynomial of (561753) and a rate of 1/2 (2,1,8). This paper proposes a new FPGA based (2, 1, 8) convolutional code decoder to address the drawbacks of high resource consumption and low maximum operating frequency in current convolutional code decoders. This decoder has a high operating frequency, low output delay, and occupies fewer resources.

VMIVME-7750-466000

The (2,1,8) convolutional code decoder implemented in this article is a hard decision decoder based on the VMIVME-7750-466000 Viterbi algorithm. The entire system is divided into three unit modules: startup unit, intermediate processing unit, and decoding output unit. The overall system structure diagram is shown in Figure 1. For the (2, 1, 8) convolutional code decoder, the starting unit processes the first 8 input codewords, and the intermediate processing unit processes the subsequent input codewords. The decoding output unit realizes the output of code words translated by the decoder. In this design, the path metrics and survival paths of each state node are stored using registers within the FPGA chip, which is achieved through register swapping. This decoding output does not require backtracking, which can greatly improve the decoding speed of the decoder.